LH5324P00A features 3,145,728 words 8 bit organization (byte mode) 1,572,864 words 16 bit organization (word mode) access time: 120 ns (max.) power consumption: operating: 440 mw (max.) standby: 1650 m w (max.) static operation ttl compatible i/o three-state outputs single +5 v power supply package: 44-pin, 600 -mil sop description the LH5324P00A is a 24m -bit mask-programmable rom organized as 3,145,728 8 bits (byte mode) or 1,572,864 16 bits (word mode) that can be selected by a byte input pin. it is fabricated using si licon- gate cmos process technology. pin connections 5324p00a-1
top view
2
3
4
5
8
9
a 2
a 5
39
38
37
36
35
34
31
28
a 7
a 6
6
7
a 3
a 4
33
32
a 10
a 11
a 13
a 15
byte
gnd
d 14
10
11
12
41
40
a 9
a 1
13
30
d 15 /a -1 (lsb)
29
d 7
oe
a 0
ce
a 12
44-pin sop
14
15
16
17
18
19
20
21
25
27
26
24
23
d 13
d 5
d 12
d 4
d 2
d 10
d 9
gnd
d 8
d 1
d 0
d 3
d 11
v cc
a 8
a 14
a 16
d 6
42
1
a 18
nc
22
44
43
a 17
a 19
a 20
figure 1. pin connect ions for sop package cmos 24m (3m 8/1.5m 16) mask-programmable rom preliminary 5-307
note: 1. the d 15 /a C1 pin becomes lsb address input (a C1 ) when the byte pin is set to be low in byte mode, and data output (d 15 ) when set to be high in word mode. 5324p00a-2
a 3
a 2
a 1
a 12
a 11
a 10
a 9
a 8
31
38
39
40
41
5
8
9
10
a 7
a 6
v cc
a 4
memory
matrix
(3,145,728 x 8)
(1,572,864 x 16)
sense amplifier
4
gnd
7
42
a 5
6
a 13
37
address buffer
a 0
11
address decoder
column selector
ce
buffer
a 14
36
a 15
35
12
timing
generator
a 16
34
a -1
d 3
d 2
d 1
d 12
d 11
d 10
d 9
d 8
d 7
d 6
d 4
d 5
d 13
d 0
d 14
d 15
data selector/output buffer
23
32
oe
buffer
address
buffer
byte/word
switchover
circuit
33
oe
ce
byte
22
20
18
16
26
19
17
15
21
30
24
25
27
29
31
14
a 17
3
a 19
43
28
a 18
2
13
a 20
44
figure 2. lh5324p 00a block diagram pin description signal pin name note a C1 C a 20 address input 1 d 0 C d 15 data output 1 byte byte/word mode switch 1 ce chip enable input signal pin name note oe output enable input v cc power supply (+5 v) gnd ground nc no connection LH5324P00A preliminary cmos 24m mask-programmable rom 5-308
truth table ce oe byte a C1 (d 15 ) data output address input supply current note d 0 C d 7 d 8 C d 15 lsb msb h x x x high-z high-z C C standby (i sb )1 l h x x high-z high-z C C operating (i cc )1 ll h C d 0 C d 7 d 8 C d 15 a 0 a 20 operating (i cc ) ll l l d 0 C d 7 high-z a C1 a 20 operating (i cc ) ll l h d 8 C d 15 high-z a C1 a 20 operating (i cc ) note: 1. x = h or l; high-z = high-impedance when the address inputs become h igh to both a 19 and a 20 , the data outputs become un specified since the data does not exist in this address area. absolute maximum ratings parameter symbol rating unit supply voltage v cc C 0.3 to +7.0 v input voltage v in C 0.3 to v cc + 0.3 v output voltage v out C 0.3 to v cc + 0.3 v operating temperature topr 0 to +70 c storage temperature tstg C 65 to +150 c recommended operating conditions (t a = 0 c to +70 c) parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v dc characterist ics (v cc = 5 v 10%, t a = 0 c to +70 c) parameter symbol con ditions min. max. unit note input high voltage v ih 2.2 v cc + 0.3 v input low voltage v il C 0.3 0.8 v output high voltage v oh i oh = C400 m a 2.4 v output low voltage v ol i ol = 2.0 ma 0.4 v input leakage current | i li | v in = 0 v to v cc 10 m a output leakage current | i lo |v out = 0 v to v cc 10 m a 1 operating current i cc1 t rc = 150 ns 80 ma 2 i cc2 t rc = 1 m s 70 standby current i sb1 ce = v ih 3ma i sb2 ce = v cc C 0.2 v 300 m a input capacitance c in f = 1 mhz t a = 25 c 10 pf output capacitance c out 10 pf notes: 1. ce/ oe = v ih 2. v in = v ih or v il , ce = v il , outputs open cmos 24m mask-programmable rom preliminary lh 5324p00a 5-309
ac characterist ics (v cc = 5 v 10%, t a = 0 c to +70 c) parameter symbol min. max. unit note read cycle time t rc 120 ns address access time t aa 120 ns chip enable access time t ace 120 ns output enable delay time t oe 60 ns output hold time t oh 5ns ce to output in high-z t chz 50 ns 1 oe to output in high-z t ohz 50 ns note: 1. this is the time required for the outputs to become high-impe dance. ac test conditions parameter rating input voltage amplitude 0.4 v to 2.6 v input rise/fall time 10 ns input reference level 1.5 v output reference level 1.5 v output load condition 1ttl + 100 pf caution to stabilize the power supply, it is recommended that a high-frequ ency bypass capacitor be connected between the v cc pin and the gnd pin. LH5324P00A preliminary cmos 24m mask-programmable rom 5-310
t oe
d 0 - d 7
t ohz
t chz
t rc
ce
t oh
data valid
t ace
t aa
oe
a -1 - a 20
note: the output data becomes valid when the last
intervals, t aa , t ace , or t oe , have concluded.
(note)
(note)
(note)
5324p00a-3
figure 3. byte mode ( byte = v il ) t oe
d 0 - d 15
t ohz
t chz
t rc
ce
t oh
data valid
t ace
t aa
oe
a 0 - a 20
note: the output data becomes valid when the last
intervals, t aa , t ace , or t oe , have concluded.
(note)
(note)
(note)
5324p00a-4
figure 4. word mode ( byte = v ih ) cmos 24m mask-programmable rom preliminary lh 5324p00a 5-311
package diagram 44-pin, 600-mil sop (sop044-p-0600)
LH5324P00A
device type
n
package
5324p00a-5
example: LH5324P00An (cmos 24m (3m x 8 or 1.5m x 16) mask-programmable rom, 44-pin, 600-mil sop)
cmos 24m (3m x 8 or 1.5m x 16) mask-programmable rom
ordering information dimensions in mm [inches]
maximum limit
minimum limit
44sop (sop044-p-0600)
16.40 [0.646]
15.60 [0.614]
13.40 [0.528]
13.00 [0.512]
14.40 [0.567]
28.40 [1.118]
28.00 [1.102]
0.15 [0.006]
1.275 [0.050]
0.25 [0.010]
0.05 [0.002]
1.275 [0.050]
2.9 [0.114]
2.5 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
typ.
44
23
22
1
3.25 [0.128]
2.45 [0.096]
44sop
2.9 [0.114]
2.5 [0.098]
1.275 [0.050]
0.25 [0.010]
0.05 [0.002]
0.80 [0.031]
0 - 10
see
detail
detail
44-pin, 600-mil sop LH5324P00A preliminary cmos 24m mask-programmable rom 5-312
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